Concept Notes (Deep Explanation + Examples)
🔹 What is an Interrupt?
An interrupt is a signal that temporarily halts the normal execution of a program to handle an urgent event.
It’s like when you’re watching a movie (main program), and suddenly your phone rings (interrupt). You pause the movie, answer the call, and then continue watching.
In embedded systems, interrupts allow microcontrollers to respond quickly to external or internal events like button presses, timers, sensors, or serial communication.
🔹 Why Interrupts?
Without interrupts, the CPU must keep checking (polling) devices to see if they need attention — wasting time.
Interrupts make systems efficient and real-time, allowing multitasking and faster response.
Example:
- A temperature sensor triggers an interrupt when temperature exceeds a threshold.
- A microcontroller (like 8051, ARM, or AVR) immediately executes a special function (Interrupt Service Routine – ISR) to control the fan.
🔹 Interrupt Sources
Interrupts can be internal or external:
- External Interrupts: Generated by external devices or pins (e.g., INT0, INT1).
Example: Push button, sensor trigger. - Internal Interrupts: Generated by on-chip peripherals.
Example: Timer overflow, ADC conversion complete, UART data received.
🔹 Interrupt Service Routine (ISR)
When an interrupt occurs:
- The current program execution pauses.
- CPU jumps to a specific memory address — the Interrupt Vector Table (IVT).
- It executes the corresponding ISR.
- After ISR completes, CPU returns to the paused task.
ISR Example (C code for 8051):
void external0_ISR(void) interrupt 0 {
P1 = 0xFF; // Example: Turn ON all LEDs on port 1
}🔹 Interrupt Priority
When multiple interrupts occur simultaneously, priority determines which is served first.
In 8051:
- Highest priority: External 0 (INT0)
- Then: Timer 0, External 1, Timer 1, Serial Interrupt.
Priority can be changed using the IP register.
🔹 Masking & Enabling Interrupts
- IE (Interrupt Enable Register): Controls which interrupts are active.
Example:
→ Enables all interrupts globally.
→ Enables external interrupt 0.
Bit format:IE = EA - - ET2 ES ET1 EX1 ET0 EX0
Example:
IE = 0x85; // Enables EX0 and Timer0 interrupts<br>🔹 Edge vs Level Triggering
- Edge-triggered: Interrupt occurs when signal changes (low → high or high → low).
- Level-triggered: Interrupt remains active as long as the signal stays at a level (e.g., low).
8051 supports both modes (controlled by TCON register).
🔹 Real-Life Embedded Examples
- IoT Sensor Node: Wakes up from sleep mode on motion detection (external interrupt).
- Smartwatch: Responds when a button is pressed.
- Communication Systems: UART interrupt when new data arrives.
- Industrial Systems: PLC detects a limit switch trigger using interrupt.
🔹 ECET Relevance
Interrupts are a top priority topic in ECET ECE — questions often test:
- ISR concept
- Priority bits
- Registers (IE, IP, TCON)
- Edge vs Level triggering
- Practical application in microcontrollers.
3️⃣ ⚙️ Formulas (Plain LaTeX, NO boxes)
4️⃣ 🔟 10 MCQs (GATE-level + ECET Mix)
1️⃣ Which register in 8051 controls enabling/disabling of interrupts?
A) TCON
B) IE
C) IP
D) SCON
2️⃣ The address of the external interrupt 0 ISR in 8051 is:
A) 0003H
B) 000BH
C) 0013H
D) 001BH
3️⃣ The function executed in response to an interrupt is called:
A) ISR
B) Subroutine
C) Main function
D) None
4️⃣ In 8051, how many interrupt sources are available?
A) 3
B) 4
C) 5
D) 6
5️⃣ Which bit enables all interrupts globally in 8051?
A) EX0
B) EA
C) ET0
D) ES
6️⃣ Which register sets the priority of interrupts in 8051?
A) IP
B) IE
C) TCON
D) PSW
7️⃣ Edge-triggered interrupt activates when:
A) Signal level is high
B) Signal changes its state
C) Signal remains low
D) CPU finishes execution
8️⃣ In interrupt handling, the time between request and ISR start is:
A) ISR Time
B) Response Time
C) Interrupt Latency
D) Context Time
9️⃣ In C, ISR function for external interrupt 0 is written as:
A) void ext0(void)
B) void external0_ISR(void) interrupt 0
C) interrupt void ISR(void)
D) void ISR(int 0)
10️⃣ If two interrupts occur simultaneously, which is served first in 8051 (default priority)?
A) Timer 0
B) Timer 1
C) External 0
D) Serial
5️⃣ ✅ Answer Key (WordPress Table Format — NO HTML)
Q.No Answer
1 B
2 A
3 A
4 C
5 B
6 A
7 B
8 C
9 B
10 C
6️⃣ 🧠 Detailed Explanations
1️⃣ B – IE:
IE (Interrupt Enable) register enables or disables specific interrupts. Example: EA enables all, EX0 enables External 0.
2️⃣ A – 0003H:
External Interrupt 0 vector address is 0003H in 8051. Each interrupt has a unique vector location.
3️⃣ A – ISR:
An Interrupt Service Routine executes automatically when the interrupt occurs.
4️⃣ C – 5:
8051 supports 5 interrupt sources (2 external, 2 timers, 1 serial).
5️⃣ B – EA:
EA bit (IE.7) is the global enable bit for all interrupts.
6️⃣ A – IP:
IP (Interrupt Priority) register sets high or low priority levels.
7️⃣ B – Signal changes its state:
Edge-triggered interrupts are activated by signal transitions.
8️⃣ C – Interrupt Latency:
Time between interrupt signal generation and start of ISR execution.
9️⃣ B – void external0_ISR(void) interrupt 0:
Correct syntax for defining ISR for INT0 in C.
10️⃣ C – External 0:
By default, External 0 (INT0) has the highest priority.
7️⃣ 🎯 Motivation / Why This Topic Matters (ECET 2026)
Interrupts form the heart of real-time embedded systems — they ensure fast response and control.
Every year, ECET asks 2–3 questions from this area, often involving registers or ISR concepts.
Mastering interrupts means mastering embedded logic, which helps you rank higher and handle both theory and practical questions confidently.
Stay consistent, revise with small examples, and your score will rise sharply.
8️⃣ 📲 CTA (Fixed)
Join our ECET 2026 ECE WhatsApp Group for daily quizzes & study notes:
👉 https://chat.whatsapp.com/GniYuv3CYVDKjPWEN086X9
