ECET 2026 CSE – Interrupts & Interrupt Cycle in Computer Organization and Architecture

Concept Notes (Deep Explanation + Examples)

🔹 What is an Interrupt?

In a computer system, an interrupt is a signal that temporarily halts the CPU’s current execution so that a more urgent task (interrupt service routine) can be handled immediately.

Think of it like this:
👉 You’re writing notes (main program), and suddenly your teacher calls your name (interrupt). You pause writing, respond to the teacher (execute ISR), and then continue your notes (resume main program).

🔹 Why Interrupts are Needed?

• To improve CPU efficiency — no need to constantly check device status (polling).
• To allow real-time handling of external or internal events.
• To support multitasking and concurrency.

🔹 Types of Interrupts

1️⃣ Hardware Interrupts – Generated by hardware devices.

• Example: Keyboard key press, mouse click, disk I/O completion.
• Signals go to Interrupt Request (IRQ) lines.

2️⃣ Software Interrupts – Triggered by executing an instruction in software.

• Example: System calls in OS, like INT 21H in assembly.

3️⃣ Internal Interrupts (Traps) – Generated automatically by CPU.

• Example: Divide by zero, overflow error, invalid opcode.

🔹 Real-World Example

💻 When you press a key on your keyboard:

• A signal (hardware interrupt) is sent to the CPU.
• CPU pauses current work.
• Executes Keyboard Interrupt Service Routine (ISR).
• Reads key code into a register.
• Returns to the previous program.

🔹 Interrupt Handling Steps (Interrupt Cycle)

Here’s how the Interrupt Cycle works, step-by-step:

1. Interrupt Request (INT):
   A device sends an interrupt signal to the CPU.
2. Acknowledgment:
   CPU acknowledges it received the interrupt.
3. Save State:
   CPU saves current program counter (PC) and status flags to the stack.
4. Vector Address Fetch:
   CPU fetches the address of the ISR (from interrupt vector table).
5. Execute ISR:
   CPU executes the interrupt service routine to handle the event.
6. Restore State:
   CPU restores PC and flags from the stack.
7. Resume Execution:
   CPU continues with the main program from where it was interrupted.

🔹 Diagram (Explained in Words)

Imagine a flow diagram like this:

Main Program
     ↓
Interrupt Occurs
     ↓
Save PC and Flags → Jump to ISR → Execute ISR
     ↓
Restore PC and Flags
     ↓
Resume Main Program

Main Program
     ↓
Interrupt Occurs
     ↓
Save PC and Flags → Jump to ISR → Execute ISR
     ↓
Restore PC and Flags
     ↓
Resume Main Program

💡 Tip: The “saving and restoring” part ensures no data or instruction is lost during the switch.

🔹 Priority and Masking

• Priority: When multiple interrupts occur, the CPU decides which one to serve first (based on priority levels).
  Example: Disk I/O > Keyboard Input.
• Masking: Some interrupts can be disabled (masked) to ignore low-priority requests temporarily.

⚙️ 3️⃣ Formulas (Plain LaTeX)

🔟 4️⃣ 10 MCQs (ECET + GATE Hybrid)

1. Which of the following best defines an interrupt?
   A) A program error
   B) A signal that temporarily halts CPU execution
   C) A compiler directive
   D) A type of memory
2. In interrupt handling, the address of ISR is stored in the:
   A) Stack
   B) Register File
   C) Interrupt Vector Table
   D) Main Memory
3. Saving the program counter during an interrupt ensures:
   A) Faster execution
   B) Program resumes from correct location
   C) Debugging is easy
   D) None
4. Software interrupts are initiated by:
   A) External devices
   B) Hardware circuits
   C) Executing a special instruction
   D) Cache
5. Maskable interrupts can be:
   A) Ignored temporarily
   B) Never ignored
   C) Triggered by CPU only
   D) None
6. In x86 processors, INT 21H is used for:
   A) Hardware interrupt
   B) DOS system call
   C) Arithmetic exception
   D) DMA request
7. The CPU checks for interrupts at:
   A) Beginning of each instruction
   B) End of each instruction cycle
   C) Random intervals
   D) When stack is empty
8. The process of giving priority to higher interrupts is called:
   A) Interrupt masking
   B) Interrupt nesting
   C) Interrupt priority
   D) Interrupt chaining
9. During ISR execution, other interrupts are:
   A) Always disabled
   B) Always enabled
   C) Depends on nesting
   D) Ignored
10. Which step is performed last in interrupt handling?
    A) Saving PC
    B) Executing ISR
    C) Restoring PC and flags
    D) Fetching ISR address

✅ 5️⃣ Answer Key

Q No | Answer
1 | B
2 | C
3 | B
4 | C
5 | A
6 | B
7 | B
8 | C
9 | C
10 | C

🧠 6️⃣ MCQ Explanations

1️⃣ B – Interrupt is a signal that halts CPU execution temporarily to handle urgent tasks.

2️⃣ C – The address of ISR is stored in the Interrupt Vector Table (IVT).

3️⃣ B – Saving PC ensures program resumes from the same location after ISR.

4️⃣ C – Software interrupts are generated by executing instructions like INT n.

5️⃣ A – Maskable interrupts can be disabled temporarily using interrupt mask bits.

6️⃣ B – INT 21H is a DOS software interrupt for system calls (file I/O, etc.).

7️⃣ B – CPU checks for interrupts at the end of each instruction cycle.

8️⃣ C – Giving precedence to higher priority interrupts is called interrupt priority.

9️⃣ C – Depending on nesting, interrupts can be enabled or disabled.

10️⃣ C – Restoring PC and flags is the final step before resuming main program.

🎯 7️⃣ Motivation (ECET 2026 Specific)

Interrupts are one of the most repeated COA topics in ECET. Every year, at least 1–2 questions come from interrupt cycle, priority, and ISR concepts.
Mastering this topic not only helps in ECET but also strengthens Operating Systems and Microprocessor understanding for higher studies.

✨ Stay consistent — learning one topic daily can make you rank-ready before others even start revision!

📲 8️⃣ CTA (Fixed)

Join our ECET 2026 CSE WhatsApp Group for daily quizzes & study notes:
👉 https://chat.whatsapp.com/GniYuv3CYVDKjPWEN086X9