Concept Notes (Deep Explanation + Examples)
Memory mapping is a fundamental concept in Computer Organization and Architecture (COA) that determines how data and instructions from main memory (RAM) are mapped into the cache memory for faster access.
Let’s understand this from a real-world example and then go deeper into ECET-level theory.
🧠 Real-Life Analogy
Imagine your main memory is like a library with 1000 books, and your cache is a small shelf with space for 10 books — only the most frequently used books are kept on that shelf.
Now the question is — how do we decide which main memory book should go to which cache slot?
That’s exactly what memory mapping techniques decide.
🧩 1. Basic Memory Hierarchy
- CPU Registers → Fastest (smallest)
- Cache Memory → Fast, small (stores recently used data)
- Main Memory (RAM) → Larger but slower
- Secondary Memory (HDD/SSD) → Largest, slowest
To speed up execution, CPU first checks cache before accessing main memory.
⚙️ 2. Memory Mapping Techniques Overview
There are 3 main types:
- Direct Mapping
- Associative Mapping
- Set-Associative Mapping
In ECET, Direct and Associative Mapping are most important.
🔹 Direct Mapping
In Direct Mapping, each block of main memory can be mapped to exactly one cache line.
🔸 Working Principle:
If main memory has m blocks and cache has n lines,
then each block i of main memory maps to cache line (i mod n).
🔸 Example:
- Main Memory = 16 blocks (0–15)
- Cache = 4 lines (0–3)
→ Block 0 → Line 0
→ Block 1 → Line 1
→ Block 2 → Line 2
→ Block 3 → Line 3
→ Block 4 → Line 0 (replaces existing)
🔸 Diagram (explained in words):
Visualize a table:
- Left: Main memory blocks 0–15
- Right: Cache lines 0–3
- Arrows show multiple main memory blocks mapping to the same cache line (conflict possible).
🔸 Disadvantage:
- Conflict Misses occur because multiple blocks compete for the same cache line.
🔸 Advantage:
- Simple and fast hardware implementation.
🔹 Associative Mapping
In Associative Mapping, any block of main memory can be placed in any cache line.
🔸 Working Principle:
There’s no fixed position. The cache stores both data and its tag (address ID) to identify which memory block it belongs to.
When CPU searches for data:
- It checks all cache lines simultaneously (using associative comparison).
🔸 Example:
- Cache has 4 lines, and memory has 16 blocks.
→ Block 5 can go to any line (0–3).
→ If cache is full, replacement policy (like LRU) decides which block to remove.
🔸 Diagram (explained in words):
Imagine a grid of cache lines with two columns:
- One for Tag (block identifier)
- One for Data
When CPU requests a block, it matches the tag with all cache lines in parallel.
🔸 Advantage:
- No conflict misses
- Flexible placement of blocks
🔸 Disadvantage:
- Complex hardware (needs parallel comparison)
- Slightly slower and costlier than direct mapping
🔍 Comparison Table (Summary)
| Feature | Direct Mapping | Associative Mapping |
|---|---|---|
| Placement | Fixed (1 block → 1 line) | Anywhere in cache |
| Flexibility | Low | High |
| Speed | Fast | Moderate |
| Conflict Miss | High | None |
| Hardware Cost | Low | High |
💡 ECET Important Tip
ECET often asks questions like:
“In direct mapping, the cache line number is found by using which operation?”
Answer: Modulo operation (Block number mod Number of lines)
Or
“In associative mapping, how does the CPU identify a block?”
Answer: By comparing tags stored in cache lines.
⚙️ Real-World Example (in CPU terms)
In modern Intel CPUs, cache memory uses a hybrid approach called Set-Associative Mapping — a balance between the simplicity of Direct Mapping and flexibility of Associative Mapping.
3️⃣ ⚙️ Formulas (Plain LaTeX, No Boxes)
where
= hit ratio
= cache access time
= main memory access time
4️⃣ 🔟 10 MCQs (ECET + GATE Hybrid)
- In direct mapping, a block from main memory maps to:
A) Any cache line
B) A specific cache line
C) A set of cache lines
D) None of these - The mapping function used in direct mapping is:
A) Addition
B) Subtraction
C) Modulo
D) Division - Associative mapping requires:
A) Tag comparison
B) Arithmetic operations
C) Logical shifting
D) None - In associative mapping, the block can be placed:
A) In a fixed cache line
B) In any cache line
C) Only in even cache lines
D) None - Direct mapping suffers from:
A) Capacity miss
B) Conflict miss
C) Compulsory miss
D) None - Associative mapping eliminates:
A) Capacity miss
B) Conflict miss
C) Compulsory miss
D) None - The tag field in associative mapping is used to:
A) Identify cache size
B) Identify memory block
C) Store parity bit
D) None - Effective access time depends on:
A) Hit ratio
B) Cache access time
C) Memory access time
D) All of these - If block number = 25 and cache lines = 8, the line number in direct mapping = ?
A) 2
B) 1
C) 3
D) 5 - Which mapping is simplest in hardware?
A) Direct
B) Associative
C) Set-associative
D) None
5️⃣ ✅ Answer Key (WordPress Table — NO HTML)
Q No | Answer
1 | B
2 | C
3 | A
4 | B
5 | B
6 | B
7 | B
8 | D
9 | A
10 | A
6️⃣ 🧠 MCQ Explanations
1️⃣ In Direct Mapping, each block maps to a fixed line → B
2️⃣ Uses Modulo operation for mapping → C
3️⃣ Associative mapping compares tags → A
4️⃣ Any cache line can be used → B
5️⃣ Conflict miss happens when multiple blocks compete → B
6️⃣ Associative mapping removes conflict misses → B
7️⃣ Tag identifies which memory block is in cache → B
8️⃣ EAT formula depends on hit ratio & times → D
9️⃣ (25 mod 8) = 1 → A
10️⃣ Direct mapping uses simple hardware → A
7️⃣ 🎯 Motivation (ECET 2026 Specific)
Memory mapping questions appear almost every year in ECET CSE Paper because they connect hardware logic with performance analysis — an area that tests conceptual depth.
If you understand this topic, you can easily score 2–3 marks in COA section.
Keep revising mapping techniques with small examples — they repeat in GATE, ECET, and PSU exams too.
8️⃣ 📲 CTA (Fixed)
Join our ECET 2026 CSE WhatsApp Group for daily quizzes & study notes:
https://chat.whatsapp.com/GniYuv3CYVDKjPWEN086X9
