Concept Notes
1. What is a Flip-Flop?
- A Flip-Flop (FF) is a bistable multivibrator → it has two stable states (0 and 1).
- It stores 1 bit of information.
- Flip-flops are sequential circuits → output depends on current input + previous state (memory).
- They are the building blocks of registers, counters, and memory devices.
2. Types of Flip-Flops
(a) SR (Set-Reset) Flip-Flop
- Inputs: S (Set), R (Reset)
- Output: Q, Q̅
- Operation:
- S = 1, R = 0 → Set (Q = 1)
- S = 0, R = 1 → Reset (Q = 0)
- S = 0, R = 0 → No change (memory)
- S = 1, R = 1 → Invalid
Characteristic Equation:
(b) JK Flip-Flop
- Modified SR FF → no invalid state.
- Inputs: J, K.
- Operation:
- J = 0, K = 0 → No change
- J = 0, K = 1 → Reset (Q = 0)
- J = 1, K = 0 → Set (Q = 1)
- J = 1, K = 1 → Toggle (Q → Q̅)
Characteristic Equation:
(c) D (Data or Delay) Flip-Flop
- Single input D, output follows input after clock.
- Operation:
- Q(next) = D
- Avoids invalid condition.
Characteristic Equation:
(d) T (Toggle) Flip-Flop
- Derived from JK FF by connecting J = K = T.
- Operation:
- T = 0 → No change
- T = 1 → Toggle (Q → Q̅)
Characteristic Equation:
3. Timing Parameters of Flip-Flops
- Setup Time (
): minimum time input must be stable before clock edge. - Hold Time (
): minimum time input must be stable after clock edge. - Propagation Delay (
): delay from input change to output change.
⚙️ Formulas
1. SR Flip-Flop Equation:
2. JK Flip-Flop Equation:
3. D Flip-Flop Equation:
4. T Flip-Flop Equation:
5. Frequency Division (Toggle FF):
🔢 Examples
Example 1:
A JK Flip-Flop has J = 1, K = 1, and present state Q = 0. Find next state.
So output toggles from 0 → 1.
Example 2:
If a T flip-flop has input T = 1 and current state Q = 1, then:
So it toggles to 0.
🔟 10 MCQs
Q1. A flip-flop can store:
a) 1 bit
b) 2 bits
c) 4 bits
d) 8 bits
Q2. The invalid condition in SR flip-flop occurs when:
a) S = 1, R = 0
b) S = 0, R = 1
c) S = 1, R = 1
d) S = 0, R = 0
Q3. The characteristic equation of JK flip-flop is:
a)
b)
c)
d)
Q4. Which flip-flop is called a “Toggle Flip-Flop”?
a) SR
b) JK
c) D
d) T
Q5. A D flip-flop always has next state equal to:
a) 0
b) 1
c) Present state
d) Input D
Q6. The output frequency of a T flip-flop with input clock 100 Hz is:
a) 100 Hz
b) 200 Hz
c) 50 Hz
d) 25 Hz
Q7. Which FF is free from invalid condition?
a) SR
b) JK
c) D
d) Both b & c
Q8. In JK FF, if J = 1 and K = 0, the next state is:
a) Reset
b) Set
c) Toggle
d) Hold
Q9. The hold time of a flip-flop is:
a) Time before clock edge input must be stable
b) Time after clock edge input must be stable
c) Total propagation delay
d) Clock pulse width
Q10. Frequency division is possible with:
a) SR FF
b) JK FF
c) D FF
d) T FF
✅ Answer Key
| Q No | Answer |
|---|---|
| Q1 | a |
| Q2 | c |
| Q3 | c |
| Q4 | d |
| Q5 | d |
| Q6 | c |
| Q7 | d |
| Q8 | b |
| Q9 | b |
| Q10 | d |
🧠 Explanations
- Q1: Flip-flop stores 1 bit.
- Q2: SR FF invalid at S = 1, R = 1.
- Q3: JK FF equation →
. - Q4: T FF is toggle FF.
- Q5: D FF follows input D.
- Q6: T FF divides clock frequency by 2 →
. - Q7: JK & D are free from invalid condition.
- Q8: J=1, K=0 → Set state.
- Q9: Hold time is minimum time input must be stable after clock edge.
- Q10: T FF used for frequency division.
🎯 Motivation
Flip-flops are fundamental memory elements in digital electronics.
- Counters, shift registers, and digital clocks are all built using FFs.
- In ECET, 5–6 questions directly test equations, truth tables, and frequency division.
👉 Mastering FFs means you can solve sequential circuit problems quickly.
📲 CTA
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